Here is what I could find for you. Thanks SKK.
EDAP = trame EDGE
It is recommended that the same timeslot allocation be used for the BSC and BTS. If required, the first EDAP timeslot at the BSC can be different than the first EDAP timeslot at the BTS. Cross connections are allowed, but it is recommended that the whole PCM frame or the n*64 cross connection complies with the ITU-T G.796 (Characteristics of a 64 kbit/s Cross-Connect Equipment with 2048 kbit/s Access Ports, Chapter 2.1) standard in respect to maintaining octet sequence integrity of signals being cross connected. The following precautions help to maximise the EDGE performance:
EDAP and the TRXs that are tied to the EDAP (including traffic/master and signaling channels) must share the same physical Abis connection route. It is also recommended that PCM frames have octet sequence integrity, which can be achieved using one of the following methods:
Using 1-3 PCM lines that perform according to G.796. If BTS capacity requires several PCM lines, a normal network delay variance between the PCM lines does not impact EDGE performance. EDAP pool and the TRXs tied to it, have to locate on a single PCM. Example 4+4+4 configuration: TRX 1-4 and their EDAP(s) on PCM1, TRX 5-8 and their EDAP(s) on PCM2, TRX 9-12 and their EDAP(s) on PCM3.
Using fractional E1, n*64k connection that complies with G.796.
The EDAP pool and TRXs tied to it must have a connection made within a single PCM or a single or multiple n*64k connection inside one PCM that comply with the G.796 in the respect of octet sequence integrity. This structure must be maintained throughout the network.
If the PCM line does not fulfill the octet sequence integrity requirement as specified in ITU-T G.796, a maximum of +/- three PCM frame delay between timeslots is tolerated when BSC software S10.5 ED CD1.2 or newer is used.
Posted by karthi